A pixel driving circuit of an active matrix driving organic light emitting diode (AMOLED) display panel generally includes at least two thin film transistors (TFT) and a storage capacitor. One of the TFTs is a switching TFT and the other one is a driving TFT. FIG. 1 is a schematic view showing a structure of a pixel of an AMOLED array substrate including a pixel driving circuit. The array substrate includes: a substrate 1; a gate electrode pattern formed on the substrate 1, the gate electrode pattern being consisted of a gate electrode 2a of a switching TFT and a gate electrode 2b of a driving TFT, as shown in the figure; a gate insulation layer 3 formed above the gate electrode pattern; an active layer pattern 4 formed above the gate insulation layer 3 in a region above the gate electrode 2a, the active layer pattern 4 being absent at a region above the gate electrode 2b; an etching stopping layer 5 formed above the active layer pattern 4 and the gate insulation layer 3; and a source and drain electrodes pattern formed above the etching stopping layer 5, the source and drain electrodes pattern including a source and drain electrodes 6a of the switching TFT and a source and drain electrodes 6b of the driving TFT. The source and drain electrodes 6a of the switching TFT is connected with the active layer pattern 4 via a source electrode via-hole A11 and a drain electrode via-hole A12 in the etching stopping layer 5, the drain electrode is connected with the active layer pattern 4 via the drain electrode via-hole A12 in the etching stopping layer 5, and the source and drain electrodes 6b of the driving TFT is connected with the gate electrode 2b via a via-hole B1 in the etching stopping layer 5. A resin layer 7 is further formed above the source and drain electrodes pattern, and a pixel electrode pattern is further formed above the resin layer 7. The resin layer 7 is provided with via-holes (not indicated in FIG. 1) at positions corresponding to the source electrode and the drain electrode of the source and drain electrodes 6a, and the resin layer 7 is also provided with a via-hole (not indicated in FIG. 1) at a position corresponding to the source and drain electrodes 6b. The pixel electrode pattern 8 is connected with the source and drain electrodes 6b through a via-hole A22 and a via-hole B2. A via-hole A21 is used to connect with a data line. When a scan line is turned on, a certain voltage is applied on the gate electrode 2a of the switching TFT such that a current flows from source electrode of the switching TFT to the drain electrode of the switching TFT, and flows to the driving TFT via the pixel electrode pattern 8 to turn on the driving TFT, and the current flows from a source electrode to a drain electrode, and the driving TFT is communicated with a storage capacitor (not shown) such that the capacitor is charged. When the scan line is turned off, voltage of in the capacitor can maintain the driving TFT at a turned-on state, and thus a constant current of the OLED can be maintained within a frame.
In prior art, there are two approaches for manufacturing the via-holes A11, A12, B1, one is as follows: after depositing the gate insulation layer 3, forming the active layer pattern 4 and depositing the etching stopping layer 5, photoresist is applied on the etching stopping layer 5, and a single patterning process is performed to form a photoresist removed region at regions above the via-holes A11, A12, B1, then a dry etching process is performed until the gate insulation layer and the etching stopping layer in a region corresponding to the via-hole B1 are completely etched off. This approach may save one patterning process. However, as a thickness that needs to be etched off in the region corresponding to the via-hole B1 is larger than a thickness that needs to be etched off in the regions corresponding to via-holes A11, A12, when a material of the etching stopping layer 5 in the regions corresponding to via-holes A11, A12 are completely etched off, the gate insulation layer 3 in the region corresponding to the via-hole B1 is not completely etched off, under the same etching process. In this instance, if the etching process is continued on the gate insulation layer 3 in the region corresponding to the via-hole B1, an upper portion of the active layer pattern 4 in the region corresponding to via-holes A11, A12 will be damaged. The other approach is as follows: after the gate insulation layer 3 is formed, a single patterning process is performed to form a via-hole in the gate insulation layer 3 in the region B1 firstly, then after the etching stopping layer 5 is formed, via-holes in the etching stopping layer 5 respectively at the regions A11, A12, B1 are formed through a single patterning process. This approach may effectively prevent the active layer pattern 4 from being damaged. However, since one more patterning process is needed, difficulty in manufacturing the array substrate is increased.